High-Reliability GPP Chip Fabrication Methods and Processes

The present invention relates to the field of semiconductor chip technology, and more particularly to a method for fabricating high-reliability glass passivation (GPP) chips.

Background Art:

GPP (glass passivation) chips are currently the mainstream in advanced technologies. The GPP process can be implemented through three primary methods: ① blade‑scraping, ② photoresist‑based patterning, and ③ electrophoretic deposition. However, each approach has its own advantages and disadvantages: blade‑scraping is low‑cost but yields non‑uniform leakage; photoresist‑based techniques offer good parameter consistency but at a higher cost; while electrophoretic deposition requires a substantial upfront investment, incurs high environmental costs, and generates waste that is difficult to manage. Today, the demands for semiconductor surface passivation are continually increasing. A GPP chip should meet the following criteria: 1) excellent electrical performance and reliability—covering resistivity, dielectric strength, ion migration rate, and other key parameters—while ensuring that the introduced materials do not introduce adverse side effects; 2) robust chemical stability, with adequate resistance to chemical corrosion; 3) ease of processing—simple procedures, good reproducibility, compatibility with device‑fabrication workflows, and a thermal expansion coefficient that matches or closely approximates that of silicon; and 4) economic viability—enabling large‑scale production, maintaining low manufacturing costs, and ensuring market competitiveness, with materials and processes that exhibit strong durability and significant development potential. Nevertheless, the GPP chips currently available on the market suffer from various issues and fail to fully satisfy these requirements.

Technical features:

1. A method for fabricating a high-reliability GPP chip, characterized by comprising the following steps:
(1) Apply photoresist to the diffused PN-junction silicon wafer.
(2) Use a mixed etchant of HF:HNO3:HAC to etch the trenches.
(3) Oxygen and ammonia are doped into the trench using LPCVD growth.
(4) Apply glass powder by scraping and sinter it;
(5) After sintering in step 4), a soft Si3N4 layer is deposited using PECVD.
(6) Perform a second lithography step and deposit a nickel layer, followed by deposition of a Ni–Si alloy; after completing the Ni–Si alloy coating, apply another nickel layer. 7) Testing;
(7) Laser scribing on the back side.

2. The high-reliability GPP chip fabrication method according to claim 1, characterized in that, in step 2), the volume ratio of HF:HNO3:HAC is 0.8–1.2:0.8–1.2:1.8–2.2, and the mass fraction concentrations of HF, HNO3, and HAC are 40–45%, 83–93%, and 33–45%, respectively. 3. The high-reliability GPP chip fabrication method according to claim 1, characterized in that, in step 3), the LPCVD growth process for doping with hydrogen and nitrogen within the trench is carried out at a temperature of 650°C–750°C.
4. The high-reliability GPP chip fabrication method according to claim 1, characterized in that step 4) comprises sintering the glass at a temperature of 820°C to 850°C under an N₂/O₂ atmosphere.
5. The high-reliability GPP chip fabrication method according to claim 1, wherein the operating conditions for step 5), PECVD, are 380°C to 420°C.
6. The high-reliability GPP chip fabrication method according to claim 1, characterized in that, in step 6), an N1–Si alloy is deposited under conditions of 580–620°C in an N2+H2 atmosphere.